I. Field of the Disclosure
The technology of the present application relates to gated diodes and their use in circuits and related methods, including protection circuits, electro-static discharge (ESD) protection circuits, and high speed or switching circuits.
II. Background
Electro-static discharge (ESD) is a major reliability issue in integrated circuits (ICs). ESD is a transient surge in voltage (negative or positive) that may induce a large current in a circuit. To protect circuits against damage from ESD surges, protection schemes attempt to provide a discharge path for both positive and negative ESD surges. Conventional diodes can be employed in ESD protection circuits to clamp the voltage of positive and negative ESD surges to shunt current and prevent excessive voltage from being applied to a protected circuit. FIG. 1 illustrates a conventional ESD protection circuit in this regard. As illustrated in FIG. 1, a voltage rail (Vdd) 10 and a ground rail (GND) 12 are provided to power a protected circuit 14. The protected circuit 14 can be any type of circuit and provided in any form desired. In this example, a terminal in the form of a signal pin 16 provides a signal path to the protected circuit 14 for providing information and/or control to the protected circuit 14. For example, the protected circuit 14 may be included in an IC, with the signal pin 16 being an externally available pin on the IC chip.
A conventional ESD protection circuit 18 may be coupled between the voltage rail 10 and ground rail 12 to protect the protected circuit 14 from ESD surges. The exemplary ESD protection circuit 18 in FIG. 1 includes two conventional diodes: a positive ESD surge diode 20 and a negative ESD surge diode 22. The positive ESD surge diode 20 and the negative ESD surge diode 22 are coupled in series. The positive ESD surge diode 20 clamps positive voltage on the signal pin 16 to one diode drop above the voltage rail 10. The negative ESD surge diode 22 clamps negative voltage on the signal pin 16 to one diode drop below the ground rail 12. A cathode (k) of the positive ESD surge diode 20 is coupled to the voltage rail 10. An anode (a) of the positive ESD diode 20 is coupled to the signal pin 16 at a node 24 on the signal path between the signal pin 16 and the protected circuit 14. A cathode (k) of the negative ESD surge diode 22 is also coupled to the node 24 on the signal path from the signal pin 16 to the protected circuit 14. An anode (a) of the negative ESD surge diode 22 is coupled to the ground rail 12.
For positive ESD surges on the signal pin 16, the positive ESD surge diode 20 will become forward biased and clamp voltage on the signal pin 16 to one diode drop above the voltage rail 10 to protect the protected circuit 14. Energy from such an ESD surge will be conducted through the positive ESD surge diode 20 in a forward biased mode and dispersed into the voltage rail 10. Appropriate ESD protection structures may be implemented (not shown) in the voltage rail 10 to eventually dissipate a positive ESD surge to the ground rail 12. For negative ESD surges on the signal pin 16, the surge is similarly dissipated. A negative ESD surge on the signal pin 16 will place the negative ESD surge diode 22 in a forward biased mode thus providing a low-impedance path relative to the protected circuit 14. Energy from the negative ESD surge will be dissipated into the ground rail 12.
Because circuits are increasingly being provided in system-on-a-chip (SOC) configurations due to higher transistor counts, providing ESD protection in SOC technologies is becoming increasingly important. SOC technologies may employ field effect transistors (FETs) that provide a relatively thin oxide gate dielectric. These relatively thin dielectrics are susceptible to destructive breakdown and damage by excessive voltages from an ESD surge event. Further, conventional diodes, such as the ESD surge diodes 20, 22 provided in FIG. 1, may not provide sufficient conduction for ESD protection in SOC technology.
To address these shortcomings in ESD protection, and for SOC technologies in particular, shallow trench isolation (STI) diodes have been provided in ESD protection circuits. Gated diodes are also being employed in ESD protection circuits. It has been shown that use of a gated diode has superior conductance per unit length as well as turn-on speed due to the transient path of its carriers. Turn-on speed of an ESD protection circuit is important for meeting charge device modeling (CDM) specifications where large amounts of current (e.g., several amps) can flow in a very small fraction of time (e.g., less than a nanosecond) during ESD events. However, even with these advantages of gated diodes, STI diodes are predominantly used in ESD protection circuits for high speed circuits. Gated diodes can unacceptably decrease performance. A gated diode has greater perimeter capacitance per unit diffusion or active length than an STI diode. This is illustrated by example in the modeling graph 26 of FIG. 2, where input capacitance (C) of a gated diode pair 28 and an STI diode pair 30 corresponding to FIG. 1 is plotted versus input voltage (V). This example assumes a 65 nanometer (nm) process. As shown, the input capacitance (C) of the gated diode pair 28, which is normalized to the maximum capacitance of the STI diode pair 30, is higher than the input capacitance (C) of the STI diode pair 30 for given voltage (V), length, and width of the diodes (approximately 8.0 and 0.45 micrometers (μm), respectively). For example, at the rail voltage (Vdd), the normalized capacitance (C) of the gated diode pair 28 is nearly 1.8 whereas the normalized capacitance (C) of the STI diode pair 30 is approximately 1.0. This equates to the gated diode pair 28 having an approximately eighty percent (80%) increase in capacitance over the STI diode pair 30 in this example.
Increased perimeter capacitance in a gated diode increases the load capacitance when the gated diode is added to a protected circuit. Increasing load capacitance can negatively affect protected circuits. For example, increased load capacitance can decrease switching times and frequency performance of a protected circuit, because charging time will be increased due to the ESD protection circuit being coupled to the protected circuit in an R-C circuit arrangement. Further, increased capacitance provided as a result of inserting an ESD protection circuit can decrease the sensitivity of radio frequency (RF) components, such as a low noise amplifier (LNA). However, use of an STI diode having a lower capacitance in an ESD protection circuit also has a trade off over a gated diode. Use of an STI diode in an ESD protection circuit can result in low CDM voltage tolerances for the protected circuit for both positive and negative surges, and especially for protected circuits and related processes employing thin oxide gate oxide dielectric devices coupled to a pad that can be found in large SOC chips.
To preserve performance, chip manufacturers and customers have had to accept the lower CDM voltage tolerances provided by use of STI diodes in ESD protection circuits, which results in greater ESD-related exposure and failures. Thus, a need exists to provide an ESD protection circuit that exhibits superior conductance and turn-on time as well as a low capacitance so as to not adversely affect performance of a protected circuit.